3 ata drive registers-mbar + 0x3a00, 1 ata drive device control register-mbar + 0x3a5c, Section 11.3.3 – Freescale Semiconductor MPC5200B User Manual

Page 377: Section 11.3.3, ata drive registers—mbar + 0x3a00, 1 ata drive device control register—mbar + 0x3a5c

MPC5200B Users Guide, Rev. 1

11-12

Freescale Semiconductor

ATA Register Interface

11.3.3

ATA Drive Registers—MBAR + 0x3A00

The ATA drive registers are physically located inside the drive controller on the ATA disk drive. The MPC5200B ATA Host Controller
provides access to these registers using the chip selects and address bits.

ATA Drive is controlled by 32-bit registers. These registers are located at an offset from MBAR of 0x3a00. Register addresses are relative to
this offset. Therefore, the actual register address is:

MBAR + 0x3A00 + register address

Hyperlinks to the ATA Drive registers are provided below:

11.3.3.1

ATA Drive Device Control Register—MBAR + 0x3A5C

Bits

Name

Description

0:19

—

Reserved

20:31

WritePtr

Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in
special cases, but this disrupts data flow integrity. Value represents the Read address
presented to the FIFO RAM.

•

ATA Drive Device Control Register (0x3A5C)

, write-only

•

ATA Drive Sector Number Register (0x3A6C)

, R/W

•

ATA Drive Alternate Status Register (0x3A5C)

, read-only

•

ATA Drive Cylinder Low Register (0x3A70)

, R/W