Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 99)

Figure 3-27: Clock Generation Circuitry
Provides a high-level view of the clock generation circuitry and clock distribution to the transceiver. In
Arria 10 variations, the TX transceiver PLL is configured outside the 40-100GbE IP core, and
clk_ref
drives the RX CDR PLL. In Arria 10 variations, you can connect a separate reference clock for the external
TX transceiver PLL.
TX
PLL
RX
PLL
PMA
clk_txmac clk_rxmac
PCS
Ethernet MAC/PHY
Static Top Level
(alt_aeu_100_top.v)
Dynamic Top Level
(.v)
clk_ref
clk_rx_recover
(in SyncE variations)
Related Information
External Transceiver PLL Required in Arria 10 Designs on page 2-19
Information about configuring and connecting the external PLLs. Includes signal descriptions.
Resets
The Low Latency 40-100GbE IP core has a single asynchronous reset signal. Asserting this signal resets
the full IP core. You must hold the reset signal asserted for several
clk_status
clock cycles to ensure
proper hold time.
You should not release the reset signal until after you observe that the reference clock is stable. If the
reference clock is generated from an fPLL, wait until after the fPLL locks.
Table 3-16: Asynchronous Reset Signal
Signal Name Direction Description
reset_async Input Low Latency 40-100GbE IP core asynchronous reset signal
In addition, the Low Latency 40-100GbE IP core has one or two of the following synchronous reset
signals:
•
reset_status
—Resets the IP core control and status interface, an Avalon-MM interface. Associated
clock is the
clk_status
clock, which clocks the control and status interface.
•
reconfig_reset
—Resets the IP core Arria 10 transceiver reconfiguration interface, an Avalon-MM
interface. Associated clock is the
reconfig_clk
, which clocks the Arria 10 transceiver reconfiguration
interface or the interface to the Stratix V transceiver reconfiguration controller.
3-54 Resets
UG-01172
2015.05.04
Altera Corporation Functional Description
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