Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 51)

error appears as a 66-bit error block that consists of eight
/E/
characters (EBLOCK_T) in the Ethernet
frame.
To direct the IP core to insert a TX error in a packet, the client should assert the TX error insertion signal
as follows, depending on the TX client interface:
• On the Avalon-ST TX client interface, assert the
l_tx_error
signal in the EOP cycle of the packet.
• On the custom streaming TX client interface, assert bit N of the
tx_error[-1:0]
signal in the
same cycle in which bit N of
din_eop[-1:0]
is asserted.
The IP core overwrites Ethernet frame data with an EBLOCK_T error block when it transmits the
Ethernet frame that corresponds to the packet EOP.
This feature supports test amd debug of your IP core. In loopback mode, when the IP core receives a
deliberately errored packet on the Ethernet link, the IP core recognizes it as a malformed packet.
Related Information
LL 40-100GbE IP Core Malformed Packet Handling on page 3-17
Low Latency 40-100GbE IP Core TX Data Bus Interfaces
This section describes the TX data bus at the user interface and includes the following topics:
Low Latency 40-100GbE IP Core User Interface Data Bus on page 3-6
Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) on page 3-7
Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) on
page 3-10
Bus Quantization Effects With Adapters on page 3-11
User Interface to Ethernet Transmission on page 3-12
Low Latency 40-100GbE IP Core User Interface Data Bus
Table 3-1: User Interface Width Depends on IP Core Variation
The Low Latency 40-100GbE IP core provides two different client interfaces: the Avalon-ST interface and a
custom interface. The Avalon-ST interface requires adapters and the custom streaming interface does not require
adapters.
Client Interface
Data Bus Width (Bits)
LL 40GbE IP Core LL 100GbE IP Core
Custom streaming interface (no
adapters)
128 256
Avalon-ST interface (with
adapters)
256 512
3-6 Low Latency 40-100GbE IP Core TX Data Bus Interfaces
UG-01172
2015.05.04
Altera Corporation Functional Description
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