Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 6)

As illustrated, on the MAC client side you can choose a wide, standard Avalon ® Streaming (Avalon-ST)
interface, or a narrower, custom streaming interface. Depending on the variant you choose, the MAC
client side Avalon Streaming (Avalon-ST) interface is either 256 or 512 bits of data mapped to either four
or ten 10.3125 Gbps transceiver PHY links, depending on data rate, or to four 25.78125 Gbps transceiver
PHY links.
The 40GbE (XLAUI) interface has 4x10.3125 Gbps links. The 100GbE (CAUI) interface has 10x10.3125
Gbps links. For Arria 10 devices only, you can configure a 40GbE 40GBASE-KR4 variation to support
Backplane Ethernet. For Arria 10 GT devices only, you can configure a 100GbE CAUI-4 option, with
4x25.78125 Gbps links.
The FPGA serial transceivers are compliant with the IEEE 802.3ba standard XLAUI, CAUI, and CAUI-4
specifications. The IP core configures the transceivers to implement the relevant specification for your IP
core variation. You can connect the transceiver interfaces directly to an external physical medium
dependent (PMD) optical module or to another device.
The IP core provides standard MAC and physical coding sublayer (PCS) functions with a variety of
configuration and status registers. You can exclude the statistics registers. If you exclude these registers,
you can monitor the statistics counter increment vectors that the IP core provides at the client side
interface and maintain your own counters.
Related Information
Low Latency 40-100GbE MAC and PHY Functional Description on page 3-2
Provides detailed descriptions of LL 40-100GbE IP core operation and functions.
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported
Features
All LL 40-100GbE IP core variations include both a MAC and a PHY, and all variations are in full-duplex
mode. These IP core variations offer the following features:
• Designed to the IEEE 802.3ba-2010 High Speed Ethernet Standard available on the IEEE website
(www.ieee.org).
• Soft PCS logic that interfaces seamlessly to Altera 10.3125 Gbps and 25.78125 Gbps serial transceivers.
• Standard XLAUI or CAUI external interface consisting of FPGA hard serial transceiver lanes operating
at 10.3125 Gbps , or the CAUI-4 external interface consisting of four FPGA hard serial transceiver
lanes operating at 25.78125 Gbps.
• Supports 40GBASE-KR4 PHY based on 64B/66B encoding with data striping and alignment markers
to align data from multiple lanes.
• Supports 40GBASE-KR4 PHY and forward error correction (FEC) option for interfacing to
backplanes.
• Supports Synchronous Ethernet (Sync-E) by providing an optional CDR recovered clock output signal
to the device fabric.
• Avalon Memory-Mapped (Avalon-MM) management interface to access the IP core control and status
registers.
• Avalon-ST data path interface connects to client logic with the start of frame in the most significant
byte (MSB) when optional adapters are used. Interface has data width 256 or 512 bits depending on the
data rate.
1-2 Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features
UG-01172
2015.05.04
Altera Corporation About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
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