Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 70
Signal Name
Direction
Description
dout_eop[
1:0]
Output
Indicates the final word of a frame in the current
clk_rxmac
cycle. If
CRC removal is disabled, this signal indicates the word with the final
CRC byte. If CRC removal is enabled, this signal indicates the final
word with data. This signal is one-hot encoded.
dout_eop_
empty[
Output
Indicates the number of empty (invalid) bytes in the end-of-packet
byte in the word indicated by
dout_eop
.
If
dout_eop[z]
has the value of 0, then the IP core sets the value of
dout_eop_empty[(z+2):z]
to 0. However, if
dout_eop[z]
has the
value of 1, then you must use the value of
dout_eop_empty[(z+2):z]
to determine the number of empty (invalid) bytes in the end-of-packet
word (and therefore, the end-of-packet byte).
For example, if you have a 100GbE IP core and you observe that in the
current
clk_rxmac
clock cycle,
dout_eop
has the value of 4'b0100 and
dout_eop_empty
has the value of 12'b000_110_000_000, you can
conclude that byte 6 in word 2 of
dout_d
is an end-of-packet byte.
dout_idle[
1:0]
Output
Indicates the words in
dout_d
that hold Idle bytes or control informa‐
tion rather than Ethernet data. This signal is one-hot encoded.
rx_error[5:0]
Output
Reports certain types of errors in the Ethernet frame whose contents
are currently being transmitted on the client interface. This signal is
valid in EOP cycles only. To ensure you can identify the corresponding
packet, you must turn on Enable alignment EOP on FCS word in the
LL 40-100GbE parameter editor.
The individual bits report different types of errors:
• Bit [0]: Malformed packet error. If this bit has the value of 1, the
packet is malformed. The IP core identifies a malformed packet
when it receives a control character that is not a terminate
character, while receiving the packet.
• Bit [1]: CRC error. If this bit has the value of 1, the IP core detected
a CRC error in the frame.
If you turn on Enable alignment EOP on FCS word, this bit and
the
rx_fcs_error
signal behave identically.
• Bit [2]: undersized payload. If this bit has the value of 1, the frame
size is between nine and 63 bytes, inclusive. The IP core does not
recognize an incoming frame of size eight bytes or less as a frame,
and those cases are not reported here.
• Bit [3]: oversized payload. If this bit has the value of 1, the frame
size is greater than the maximum frame size programmed in the
MAX_RX_SIZE_CONFIG
register at offset 0x506.
• Bit [4]: payload length error. If this bit has the value of 1, the
payload received in the frame did not match the length field value,
and the value in the length field is less than 1536 bytes. This bit only
reports errors if you set bit [0] of the
CFG_PLEN_CHECK
register at
offset 0x50A to the value of 1.
• Bit [5} Reserved.
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming
Interface)
3-25
Functional Description
Altera Corporation