Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 166
Word Addr
Bit
R/W
Name
Description
0x4C2
8
RO
FEC negotiated –
enable FEC from SEQ
When set to 1, PHY is negotiated to perform FEC.
When set to 0, PHY is not negotiated to perform
FEC.
9
RO
Seq AN Failure
When set to 1, a sequencer Auto Negotiation
failure has been detected. When set to 0, an Auto
Negotiation failure has not been detected.
17:12
RO
KR AN Link
Ready[5:0]
Provides a one-hot encoding of an_receive_idle =
true and link status for the supported link as
described in Clause 73.10.1. The following
encodings are defined:
• 6'b000000: 1000BASE-KX
• 6'b000001: 10GBASE-KX4
• 6'b000100: 10GBASE-KR
• 6'b001000: 40GBASE-KR4
• 6'b010000: 40GBASE-CR4
• 6'b100000: 100GBASE-CR10
UG-01172
2015.05.04
10GBASE-KR PHY Register Definitions
B-7
Arria 10 10GBASE-KR Registers
Altera Corporation