Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 2)

Contents
About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY
MegaCore Function.........................................................................................1-1
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features................... 1-2
Low Latency 40-100GbE IP Core Device Family and Speed Grade Support...................................... 1-4
Device Family Support....................................................................................................................1-4
Low Latency 40-100GbE IP Core Device Speed Grade Support...............................................1-5
IP Core Verification.....................................................................................................................................1-5
Simulation Environment................................................................................................................ 1-6
Compilation Checking.................................................................................................................... 1-6
Hardware Testing.............................................................................................................................1-6
Performance and Resource Utilization.....................................................................................................1-6
Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores.....................................1-7
Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores...................................... 1-8
Release Information...................................................................................................................................1-10
Getting Started.................................................................................................... 2-1
Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices......................................2-2
Installing and Licensing IP Cores..............................................................................................................2-3
OpenCore Plus IP Evaluation........................................................................................................ 2-3
Specifying the Low Latency 40-100GbE IP Core Parameters and Options.........................................2-3
IP Core Parameters......................................................................................................................................2-5
Files Generated for Stratix V Variations.................................................................................................2-13
Files Generated for Arria 10 Variations..................................................................................................2-14
Integrating Your IP Core in Your Design.............................................................................................. 2-17
Pin Assignments.............................................................................................................................2-18
External Transceiver Reconfiguration Controller Required in Stratix V Designs............... 2-18
External Transceiver PLL Required in Arria 10 Designs......................................................... 2-19
External Time-of-Day Module for Variations with 1588 PTP Feature..................................2-20
Clock Requirements for 40GBASE-KR4 Variations.................................................................2-21
External TX MAC PLL..................................................................................................................2-21
Placement Settings for the Low Latency 40-100GbE IP Core................................................. 2-21
Low Latency 40-100GbE IP Core Testbenches......................................................................................2-21
Low Latency 40-100GbE IP Core Testbench Overview........................................................... 2-22
Understanding the Testbench Behavior..................................................................................... 2-26
Simulating the Low Latency 40-100GbE IP Core With the Testbenches.......................................... 2-27
Generating the Low Latency 40-100GbE Testbench................................................................ 2-28
Optimizing the Low Latency 40-100GbE IP Core Simulation With the Testbenches.........2-29
Simulating with the Modelsim Simulator...................................................................................2-29
Simulating with the NCSim Simulator....................................................................................... 2-30
Simulating with the VCS Simulator............................................................................................ 2-30
Testbench Output Example: Low Latency 40-100GbE IP Core..............................................2-30
TOC-2 About The Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
Altera Corporation