Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 62)

Low Latency 40-100GbE IP Core RX Filtering
The Low Latency 40-100GbE IP core processes all incoming valid frames. However, the IP core does not
forward pause frames to the Avalon-ST RX client interface by default.
If you set the
cfg_fwd_ctrl
bit of the
RX_PAUSE_FWD
register to the value of 1, the IP core forwards pause
frames to the Avalon-ST RX client interface.
40-100GbE IP Core Preamble Processing
The preamble sequence is Start, six preamble bytes, and SFD. If this sequence is incorrect the frame is
ignored. The Start byte must be on receive lane 0 (most significant byte). The IP core uses the SFD byte
(0xD5) to identify the last byte of the preamble. The MAC RX looks for the Start, six preamble bytes and
SFD.
By default, the MAC RX removes all Start, SFD, preamble, and IPG bytes from accepted frames. However,
if you turn on Enable preamble passthrough in the Low Latency 40-100GbE parameter editor, the MAC
RX does not remove the eight-byte preamble sequence.
40-100GbE IP Core FCS (CRC-32) Removal
Independent user configuration register bits control FCS CRC removal at runtime. CRC removal supports
both narrow and wide bus options. Bit 0 of the
MAC_CRC_CONFIG
register enables and disables CRC
removal; by default, CRC removal is enabled.
In the user interface, the EOP signal (
l_rx_endofpacket
or
dout_eop
) indicates the end of CRC
bytes if CRC is not removed. When CRC is removed, the EOP signal indicates the final byte of payload.
The IP core signals an FCS error by asserting the FCS error output signal
l_rx_fcs_error
and the
l_rx_fcs_valid
(or
rx_fcs_error
and the
rx_fcs_valid
) output signals in the same clock cycle.
The
l_rx_error[1]
or
rx_error[1]
also signals an FCS error.
If you turn on Enable alignment EOP on FCS word in the parameter editor, the IP core asserts
l_rx_fcs_error
(or
rx_fcs_error
) and the EOP signal on the same clock cycle if the current frame
has an FCS error. However, if you turn off Enable alignment EOP on FCS word, the IP core asserts
l_rx_fcs_error
in a later clock cycle than the EOP signal.
40-100GbE IP Core CRC Checking
The 32-bit CRC field is received in the order: X32, X30, . . . X1, and X0 , where X32 is the most significant
bit of the FCS field and occupies the least significant bit position in the first FCS byte.
If a CRC32 error is detected, the RX MAC marks the frame invalid by asserting the
l_rx_fcs_error
and
l_rx_fcs_valid
(or
rx_fcs_error
and
rx_fcs_valid
) signals, as well as the
l_rx_error[1]
(or
rx_error[1]
) signal.
LL 40-100GbE IP Core Malformed Packet Handling
While receiving an incoming packet from the Ethernet link, the LL 40-100GbE IP core expects to detect a
terminate character at the end of the packet. When it detects an expected terminate character, the IP core
generates an EOP on the client interface. However, sometimes the IP core detects an unexpected control
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core RX Filtering 3-17
Functional Description Altera Corporation
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