Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 127
Address
Name
Bit
Description
HW
Reset
Value
Access
LT VPre ovrd
Enable, Lane
0
[29]
When set to 1, enables the override value for the
VPRERULE parameter stored in the
LT VPre
ovrd, Lane 0
register field.
1 for
simula
tion; 0
for
compil
ation
RW
0xE0
Register 0xD3 refers to Lane 0. This register, register 0xE0, is the equivalent of
register 0xD3 for Lane 1 link training.
RW
0xE1
Register 0xD4 refers to Lane 0. This register, register 0xE1, is the equivalent of
register 0xD4 for Lane 1 link training.
RW
0xE2
Register 0xD5 refers to Lane 0. This register, register 0xE2, is the equivalent of
register 0xD5 for Lane 1 link training.
RO
0xE3
Register 0xD6 refers to Lane 0. This register, register 0xE3, is the equivalent of
register 0xD6 for Lane 1 link training..
RW
0xE4
This register is the equivalent of register 0xD3 for Lane 2 link training.
RW
0xE5
This register is the equivalent of register 0xD4 for Lane 2 link training.
R / RW
0xE6
This register is the equivalent of register 0xD5 for Lane 2 link training.
RO
0xE7
This register is the equivalent of register 0xD6 for Lane 2 link training.
RW
0xE8
This register is the equivalent of register 0xD3 for Lane 3 link training.
RW
0xE9
This register is the equivalent of register 0xD4 for Lane 3 link training.
R / RW
0xEA
This register is the equivalent of register 0xD5 for Lane 3 link training.
RO
0xEB
This register is the equivalent of register 0xD6 for Lane 3 link training.
RW
Related Information
The 40GBASE-KR4 variations of the 40-100GbE IP core use the 10GBASE-KR PHY IP core PHY registers
at internal offsets 0xB0–0xFF (at IP core register map offsets 0xB0–0xFF), in addition to the registers
listed in this section. Information about this PHY IP core, including register descriptions, is available in
the Backplane Ethernet 10GBASE-KR PHY IP Core with FEC Option chapter of the Altera Transceiver
PHY IP Core User Guide..
3-82
LL 40GBASE-KR4 Registers
UG-01172
2015.05.04
Altera Corporation
Functional Description