Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 66
Name
Direction
Description
l
Output
Reports certain types of errors in the Ethernet frame
whose contents are currently being transmitted on the
client interface. This signal is valid in EOP cycles only. To
ensure you can identify the corresponding packet, you
must turn on Enable alignment EOP on FCS word in the
LL 40-100GbE parameter editor.
The individual bits report different types of errors:
• Bit [0]: Malformed packet error. If this bit has the value
of 1, the packet is malformed. The IP core identifies a
malformed packet when it receives a control character
that is not a terminate character, while receiving the
packet.
• Bit [1]: CRC error. If this bit has the value of 1, the IP
core detected a CRC error in the frame.
If you turn on Enable alignment EOP on FCS word,
this bit and the
l
signal behave
identically.
• Bit [2]: undersized payload. If this bit has the value of
1, the frame size is between nine and 63 bytes,
inclusive. The IP core does not recognize an incoming
frame of size eight bytes or less as a frame, and those
cases are not reported here.The
l
or
rx_error[1]
also signals an FCS error.
• Bit [3]: oversized payload. If this bit has the value of 1,
the frame size is greater than the maximum frame size
programmed in the
MAX_RX_SIZE_CONFIG
register at
offset 0x506.
• Bit [4]: payload length error. If this bit has the value of
1, the payload received in the frame did not match the
length field value, and the value in the length field is
less than 1536 bytes. This bit only reports errors if you
set bit [0] of the
CFG_PLEN_CHECK
register at offset
0x50A to the value of 1.
• Bit [5} Reserved.
l
Output
When asserted, indicates that RX data is valid. Only valid
between the
l
and
l
endofpacket
signals.
l
Output
When asserted, indicates that FCS is valid.
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core RX Data Bus
3-21
Functional Description
Altera Corporation