Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 57)

Figure 3-7: Reduced Bandwidth With Left-Aligned SOP Requirement
Illustrates the reduction of bandwidth that would be caused by left-aligning the SOP for the 100GbE IP
core.
Three unusable words
The example shows a nine-word packet, which is the worst case for bandwidth utilization. Assuming
another packet is waiting for transmission, the effective ingress bandwidth is reduced by 25%. Running
the MAC portion of the logic slightly faster than is required can mitigate this loss of bandwidth.
Additional increases in the MAC frequency can provide further mitigation, although increases in
frequency make timing closure more difficult. The wider data bus for the Avalon-ST interface also helps
to compensate for the Avalon-ST left-aligned SOP requirement.
User Interface to Ethernet Transmission
The IP core reverses the bit stream for transmission per Ethernet requirements. The transmitter handles
the insertion of the inter-packet gap, frame delimiters, and padding with zeros as necessary. The
transmitter also handles FCS computation and insertion.
The Ethernet MAC and PHY transmit complete packets. After transmission begins, it must complete with
no IDLE insertions. Between the end of one packet and the beginning of the next packet, the data input is
not considered and the transmitter sends IDLE characters. An unbounded number of IDLE characters
can be sent between packets.
Order of Transmission
The IP core transmits bytes on the Ethernet link starting with the preamble and ending with the FCS in
accordance with the IEEE 802.3 standard. Transmit frames the IP core receives on the client interface are
big-endian. Frames the MAC sends to the PHY on the XGMII/CGMII between the MAC and the PHY are
little-endian; the MAC TX transmits frames on this interface beginning with the least significant byte.
Figure 3-8: Byte Order on the Client Interface Lanes Without Preamble Pass‑Through
Describes the byte order on the Avalon-ST interface when the preamble pass-through feature is turned
off. Destination Address[40] is the broadcast/multicast bit (a type bit), and Destination Address[41] is a
locally administered address bit.
Destination Address (DA) Source Address (SA) Data (D)
Type/
Length
Octet 5 4 3 1 2 0 5 4 3 0 1 2 1 0 00 ... NN
Bit
[47
:40]
[39
:32]
[31
:24]
[23
:16]
[15
:8]
[7:
0]
[47
:40]
[39
:32]
[31
:24]
[23
:16]
[15
:8]
[7:
0]
[15
:8]
[7:
0]
MSB[7
:0]
...
LSB[
7:0]
3-12 User Interface to Ethernet Transmission
UG-01172
2015.05.04
Altera Corporation Functional Description
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