Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 160)

Arria 10 10GBASE-KR Registers
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2015.05.04
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This appendix duplicates the 10GBASE-KR PHY register listings from the Arria 10 Transceiver PHY
User Guide . Altera provides this appendix as a convenience to make the full LL 40GBASE-KR4 register
information available in the LL 40-100GbE IP core user guide. While Altera makes every attempt to keep
the information in the appendix up-to-date, the most up-to-date information is always found in the Arria
10 Transceiver PHY User Guide , and the appendix is not guaranteed to be up-to-date at any particular
time.
Most LL 40GBASE-KR4 registers are 10GBASE-KR PHY registers of the Arria 10 10GBASE-KR PHY IP
core, documented in the Arria 10 Transceiver PHY User Guide and duplicated, with a potential time lag
for updates, in this appendix. The register offsets differ by 0x400 in the 40GBASE-KR4 variations of the
40-100GbE IP core. The LL 40GBASE-KR4 variations of the LL 40-100GbE IP core have additional LL
40GBASE-KR4 related registers and register fields.
LL 40GBASE-KR4 Registers documents the differences between the 10GBASE-KR PHY register
definitions in the 10GBASE-KR PHY Register Defintions section of the 10GBASE-KR PHY IP Core section
in the Arria 10 Transceiver PHY User Guide and the 40GBASE-KR4 registers of the Low Latency
40-100GbE IP core. All Arria 10 10GBASE-KR PHY registers and register fields not listed in LL
40GBASE-KR4 Registers are available in the 40GBASE-KR4 variations of the LL 40-100GbE IP core.
Where the Arria 10 Transceiver PHY User Guide and this appendix list 10GBASE-R, substitute 40GBASE-
KR4 with auto-negotiation and link training both turned off, and where they list 10GBASE-KR (except in
the description of 0x4CB[24:0]), substitute 40GBASE-KR4. Where a register field description in the Altera
Transceiver PHY IP Core User Guide and this appendix refers to link training or FEC in the single-lane
10GBASE-KR PHY IP core, substitute link training or FEC on Lane 0 of the LL 40GBASE-KR4 IP core
variation.
Related Information
Arria 10 Transceiver PHY User Guide
The 40GBASE-KR4 variations of the LL 40-100GbE IP core use the 10GBASE-KR PHY IP core PHY
registers at internal offsets 0x4B0–0x4FF (at IP core register map offsets 0xB0–0xFF), in addition to the
registers listed in LL 40GBASE-KR4 Registers . Information about this PHY IP core, including up-to-date
register descriptions, is available in the 10GBASE-KR PHY IP Core section of the Arria 10 Transceiver
PHY User Guide..
10GBASE-KR PHY Register Definitions
The Avalon-MM slave interface signals provide access to the control and status registers.
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