Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 134)

Addr Name Bit Description HW Reset
Value
Access
0x60A if
you set the
value of
Flow
control
mode to
Standard
flow
control in
the LL 40-
100GbE
parameter
editor.
TX_XOF_EN
[0]
Enable the TX MAC to pause outgoing
Ethernet traffic in response to a pause frame
received on the RX Ethernet link and
forwarded to the TX MAC by the RX MAC.
If the
cfg_enable
bit of the
RX_PAUSE_
ENABLE
register has the value of 1, the RX
MAC processes incoming pause frames.
When the RX MAC processes an incoming
pause frame with an address match, it notifies
the TX MAC to pause outgoing traffic on the
TX Ethernet link. The TX MAC pauses
outgoing traffic on the TX Ethernet link in
response to this notification only if bit [0] of
the
TX_XOF_EN
register has the value of 1.
The value in the
TX_XOF_EN
register is only
relevant when the
cfg_enable
bit of the
RX_
PAUSE_ENABLE
register has the value of 1. If
the
cfg_enable
bit of the
RX_PAUSE_ENABLE
register has the value of 0, pause frames
received on the RX Ethernet link do not
reach the TX MAC.
1'b0 RW
0x60A if
you set the
value of
Flow
control
mode to
Priority-
based
flow
control in
the LL 40-
100GbE
parameter
editor.
TX_PAUSE_
QNUMBER
[2:0] Queue number (index to internal table) of
queue whose relevant values are currently
accessible (readable and writeable) in these
registers:
•
RETRANSMIT_XOFF_HOLDOFF_QUANTA
at
offset 0x608
•
TX_PAUSE_QUANTA
at offset 0x609
0 RW
UG-01172
2015.05.04
Pause Registers 3-89
Functional Description Altera Corporation
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