Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 188)

Date Compatible ACDS
Version
Changes
• Added new TX error insertion feature. User logic can direct the IP
core to insert an error in an outgoing Ethernet frame, using the new
l_tx_error
and
tx_error
input signals on the TX client
interface. Refer to Low Latency 40-100GbE IP Core TX Data Bus
with Adapters (Avalon-ST Interface) on page 3-7 and Low
Latency 40-100GbE IP Core TX Data Bus Without Adapters
(Custom Streaming Interface) on page 3-10, and to new section
Error Insertion Test and Debug Feature on page 3-5.
• Updated description of priority-based flow control. Priority-based
flow control is now available for both LL 40GbE IP core variations
and LL 100GbE IP core variations. Previously it was available only
in LL 100GbE variations.
• Added new signal
tx_lanes_stable
, in PHY Status Interface on
page 3-48.
• Updated description of the
rx_ctle_mode
40GBASE-KR4 register
and added default value for
Enable Arria 10 Calibration
40GBASE-KR4 register. Also corrected the bit range of the
LP
Coefficients Update
register field. For these changes and other
40GBASE-KR4 register information specific to this IP core, refer to
LL 40GBASE-KR4 Registers on page 3-71. For changes to the
underlying Arria 10 10GBASE-KR PHY registers, refer to the Arria
10 Transceiver PHY User Guide or to the Arria 10 10GBASE-KR
Registers on page 6-1 appendix.
• Corrected the addresses of the
CNTR_TX_STATUS
and
CNTR_RX_
STATUS
registers.
• Corrected the descriptions of the
PHY_PCS_INDIRECT_ADDR
and
PHY_PCS_INDIRECT_DATA
registers at offsets 0x314 and 0x315.
• Added note recommending that designs with multiple LL 40-
100GbE IP cores not use the ATX PLL HDL code that is currently
provided with the IP core. This code is deprecated. Refer to
External Transceiver PLL Required in Arria 10 Designs on page
2-19.
• Added clock information for multiple IP core top-level signals.
• Added information about how to check for word lock and
alignment marker lock, in Debugging the 40GbE and 100GbE
Link on page 4-1.
• Updated Differences Between Low Latency 40-100GbE IP Core
and 40-100GbE IP Core v15.0 appendix with information about
the v15.0 IP core.
• Clarified the different paths to the example design and testbench
directories and scripts in variations that target different device
families.
• Added description of the
AM_CNT_BITS
parameter in Optimizing
the Low Latency 40-100GbE IP Core Simulation With the
Testbenches on page 2-29. You might need to modify this
parameter in your own simulation environment.
D-2 Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User
Guide Revision History
UG-01172
2015.05.04
Altera Corporation Additional Information
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