Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 121)

Address Name Bit Description HW
Reset
Value
Access
Ovride LP
Coef Enable
[16] When set to 1, overrides the link partner's
equalization coefficients; software changes the
update commands sent to the link partner TX
equalizer coefficients. When set to 0, uses the
Link Training logic to determine the link partner
coefficients. Used with 0x0D1 bits [7:4] and
bits[7:0] of 0x0D4 through 0x0D7.
1'b0 RW
Ovride Local
RX Coef
Enable
[17] When set to 1, overrides the local device
equalization coefficients generation protocol.
When set, the software changes the local TX
equalizer coefficients. When set to 0, uses the
update command received from the link partner
to determine local device coefficients. Used with
0x0D1 bits [11:8] and bits[23:16] of 0x0D4
through 0x0D7.
1'b0 RW
Reserved [19:18
]
Reserved
rx_ctle_mode
[21:20
]
Defines at what point to enable the RX CTLE in
the adaptation algorithm. The following values
are defined:
• 00 = never, the RX CTLE isn’t enabled or
adjusted.
• 01 = trigger CTLE before starting TX
equalization.
• 10 = trigger CTLE after completing TX
equalization.
• 11 = trigger CTLE before starting TX
equalization and again after completing TX
equalization.
2'b11
Reserved [31:22
]
Reserved
0x0D1
Restart Link
training,
Lane 1
[1]
When set to 1, resets the 40GBASE-KR4 start-up
protocol. When set to 0, continues normal
operation. This bit self clears. Refer to the state
variable
mr_restart_training
as defined in
Clause 72.6.10.3.1 and 10GBASE-KR PMD
control register bit (1.150.0) in IEEE Std 802.3ap-
2007.
Register bit 0xD1[0] refers to Lane 0. This bit is
the equivalent of register 0xD1[0] for Lane 1.
1'b0
RW SC
Restart Link
training,
Lane 2
[2]
This bit is the equivalent of register 0xD1[0] for
Lane 2.
1'b0
RW SC
3-76 LL 40GBASE-KR4 Registers
UG-01172
2015.05.04
Altera Corporation Functional Description
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