Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 50)

provides the length of the payload data that ranges from 0–1500 bytes. The TX MAC does not modify this
field before forwarding it to the network.
Frame Padding
When the length of client frame is less than 64 bytes (meaning the payload is less than 46 bytes) and
greater than eight bytes, the TX MAC module inserts pad bytes (0x00) after the payload to create a frame
length equal to the minimum size of 64 bytes.
Caution: The Low Latency 40-100GbE IP core does not process incoming (egress) frames of less than
nine bytes correctly. You must ensure such frames do not reach the TX client interface.
Frame Check Sequence (CRC-32) Insertion
The TX MAC computes and inserts a CRC32 checksum in the transmitted MAC frame. The frame check
sequence (FCS) field contains a 32-bit CRC value. The MAC computes the CRC32 over the frame bytes
that include the source address, destination address, length, data, and pad (if applicable). The CRC
checksum computation excludes the preamble, SFD, and FCS. The encoding is defined by the following
generating polynomial:
FCS(X) = X32 +X26 +X23 +X22 +X16 +X12 +X11 +X10 +X8 +X7 +X5 +X4 +X2 +X1 +1
CRC bits are transmitted with MSB (X32) first.
If you configure your Low Latency 40-100GbE IP core with no flow control, you can configure your IP
core TX MAC to implement TX CRC insertion or not, by turning Enable TX CRC insertion on or off in
the Low Latency 40-100GbE parameter editor. By default, the CRC insertion feature is enabled. In
variations with flow control, CRC insertion is enabled.
Related Information
Order of Transmission on page 3-12
Illustrations of the byte order and octet transmission order on the Avalon-ST client interface.
Inter‑Packet Gap Generation and Insertion
If you set Average interpacket gap to 12 in the Low Latency 40-100GbE parameter editor, the TX MAC
maintains the minimum inter-packet gap (IPG) between transmitted frames required by the IEEE 802.3
Ethernet standard. The standard requires an average minimum IPG of 96 bit times (or 12 byte times). The
deficit idle counter maintains the average IPG of 12 bytes.
If you set Average interpacket gap to 8, the TX MAC maintains a minimum average IPG of 8 bytes. This
option is provided as an intermediate option to allow you to enforce an IPG that does not conform to the
Ethernet standard, but which increases the throughput of your IP core.
If you set Average interpacket gap to Disable deficit idle counter, the IP core transmits Ethernet packets
as soon as the data is available, without maintaining the 12-byte IPG. In this case the IP core maintains
only a minimum 1-byte IPG. If you select this parameter value, you optimize the IP core throughput.
Error Insertion Test and Debug Feature
The client can specify the insertion of a TX error in a specific packet. If the client specifies the insertion of
a TX error, the LL 40-100GbE IP core inserts an error in the frame it transmits on the Ethernet link. The
UG-01172
2015.05.04
Frame Padding 3-5
Functional Description Altera Corporation
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