Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 107
Signal Name
Direction
Interface
status_addr[15:0]
Input
Control and status interface
status_read
Input
status_write
Input
status_writedata[31:0]
Input
status_readdata[31:0]
Output
status_readdata_valid
Output
status_waitrequest
Output
status_read_timeout
Output
tod_txmac_in[95:0]
Input
1588 PTP interface
These signals are available only if
1588 PTP functionality is
included in the IP core.
tod_rxmac_in[95:0]
Input
tx_in_zero_tcp
Input
tx_in_tcp_offset[15:0]
Input
tx_in_ptp
Input
1588 PTP interface
These signals are available in
new IP core variations that
include 588 PTP functionality. In
IP core variations that do not
include 588 PTP functionality,
but which you upgraded to the
v14.1 IP core, these signals are
present but unused, and the
output signals are tied low..
tx_in_ptp_overwrite[1:0]
Input
tx_in_ptp_offset[15:0]
Input
ptp_pkt_out
Output
tod_tx_clk_st2[95:0]
Output
rx_tod[95:0]
Output
reconfig_to_xcvr[559:0]
(40GbE)
reconfig_to_xcvr[1399:0]
(100GbE)
Input
Interface to Stratix V reconfigu‐
ration controller
These signals are available in
Stratix V devices only.
reconfig_from_xcvr[367:0]
(40GbE)
reconfig_from_xcvr[919:0]
(100GbE)
Output
reconfig_busy
Input
3-62
Low Latency 40-100GbE IP Core Signals
UG-01172
2015.05.04
Altera Corporation
Functional Description