Low latency 100gbe caui–4 phy, External reconfiguration controller, External transceiver pll – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 72: External tx mac pll, Low latency 100gbe caui–4 phy -27, External reconfiguration controller -27, External transceiver pll -27, External tx mac pll -27
Related Information
•
Low Latency 40-100GbE IP Core MAC Configuration Registers
on page 3-83
Describes the
MAX_RX_SIZE_CONFIG
and
CFG_PLEN_CHECK
registers.
•
on page 3-19
Low Latency 100GbE CAUI–4 PHY
The Low Latency 100GbE PHY IP core configured in an Arria 10 GT device supports CAUI-4 PCS and
PMA at 4 x 25.78125 Gbps.
Related Information
Low Latency 40-100GbE IP Core Device Speed Grade Support
Information about the device speed grades that support the 100GbE CAUI–4 IP core variation.
External Reconfiguration Controller
Low Latency 40GbE and 100GbE IP cores that target a Stratix V device require an external reconfigura‐
tion controller.
Altera recommends that you configure an Altera Transceiver Reconfiguration Controller for your Stratix
V 40-100GbE IP core.
Related Information
External Transceiver Reconfiguration Controller Required in Stratix V Designs
Information about configuring and connecting the Altera Transceiver Reconfiguration Controller.
Includes signal descriptions.
External Transceiver PLL
Low Latency 40GbE and 100GbE IP cores that target an Arria 10 device require an external transceiver
PLL. The number and type of transceiver PLLs your design requires depends on the transceiver channels
and available clock networks.
Related Information
•
External Transceiver PLL Required in Arria 10 Designs
on page 2-19
Information about configuring and connecting the external PLLs. Includes signal descriptions.
•
Low Latency 40-100GbE IP Core Example Project
The Arria 10 example project provides an example of how to connect external PLLs to your Arria 10
Low Latency 40-100GbE IP core.
•
Information about the correspondence between transceiver PLLs and transceiver channels, and
information about how to configure an external transceiver PLL for your own design.
External TX MAC PLL
If you turn on Use external TX MAC PLL in the LL 40-100GbE parameter editor, the IP core has an extra
input port,
clk_txmac_in
, which drives the TX MAC clock. You must connect this input port to a clock
source, usually a PLL on the device.
UG-01172
2015.05.04
Low Latency 100GbE CAUI–4 PHY
3-27
Functional Description
Altera Corporation