Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 119)

Address Name Bit Description HW
Reset
Value
Access
RCLR_
ERRBLK_
CNT, Lane 0
12 Writing a 1 resets the error block
counters.Writing a 0 causes counting to resume.
Each lane has a 32-bit corrected error block
counter and a 32-bit uncorrected error block
counter in the Arria 10 device registers. Refer to
Clause 74.8.4.1 and Clause 74.8.4.2 of IEEE Std
802.3ap-2007.
For Lane 0, the corrected error block counter is
in the Arria 10 device registers you access
through the Arria 10 dynamic reconfiguration
interface at offsets 0xDC to 0xDF:
blkcnt_
corr[31:0]
is in {0xDF[7:0],0xDE[7:0],
0xDD[7:0],0xDC[7:0]}.
For Lane 0, the uncorrected error block counter
is in the Arria 10 device registers you access
through the Arria 10 dynamic reconfiguration
interface at offsets 0xE0 to 0xE3:
blkcnt_
uncorr[31:0]
is in {0xE3[7:0],0xE2[7:0],
0xE1[7:0],0xE0[7:0]}.
RW
Reserved [31:13
]
Reserved
0x0B5
Register 0xB2 refers to Lane 0. This register is the equivalent of register 0xB2 for
Lane 1. The relevant FEC error Arria 10 device registers for Lane 1 are at 0x4BD
through 0x4E3 (additional offset of 0x400).
RW
0x0B8
This register is the equivalent of register 0xB2 for Lane 2. The relevant FEC error
Arria 10 device registers for Lane 2 are at 0x8BD through 0x8E3 (additional offset
of 0x800 compared to the Lane 0 device registers).
RW
0x0BB
This register is the equivalent of register 0xB2 for Lane 3. The relevant FEC error
Arria 10 device registers for Lane 3 are at 0xCBD through 0xCE3 (additional offset
of 0xC00 compared to the Lane 0 device registers).
RW
0x0C0 Override AN
Channel
Enable
[6]
Overrides the auto-negotiation master channel
that you set with the Auto-Negotiation Master
parameter, setting the new master channel
according to the value in register 0xCC[3:0].
While 0x0C0[6] has the value of 1, the channel
encoded in 0xCC[3:0] is the master channel.
While 0xC0[6] has the value of 0, the master
channel is the channel that you set with the
Auto-Negotiation Master parameter.
1'b0
RW
0x0C2 KR4 AN Link
Ready [5:0]
[17:12
]
Provides a one-hot encoding of an_receive_idle
= true and link status for the supported link as
described in Clause 73.10.1. The following
encodings are defined:
6'b001
000
RO
3-74 LL 40GBASE-KR4 Registers
UG-01172
2015.05.04
Altera Corporation Functional Description
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