Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 26)

Parameter Type Range Default
Setting
Parameter Description
Enable Link
Training
Boolean • True
• False
True If this parameter is turned on, the IP core includes
the link training module, which configures the
remote link partner TX PMD for the lowest Bit Error
Rate (BER). LT is defined in Clause 72 of IEEE Std
802.3ap–2007.
Maximum bit
error count
Integer
2 n – 1 for
n an
integer in
the range
4–10.
511
Specifies the maximum number of errors on a lane
before the
Link Training Error
bit (40GBASE-
KR4 register offset 0xD2, bit 4, 12, 20, or 28,
depending on the lane) is set, indicating an unaccept‐
able bit error rate.
n is the width of the Bit Error Counter that is
configured in the IP core. The value to which you set
this parameter determines n, and thus the width of
the Bit Error Counter. Because the default value of
this parameter is 511, the default width of the Bit
Error Counter is 10 bits.
You can use this parameter to tune PMA settings. For
example, if you see no difference in error rates
between two different sets of PMA settings, you can
increase the width of the bit error counter to
determine if a larger counter enables you to
distinguish between PMA settings.
Number of
frames to send
before sending
actual data
Integer • 127
• 255
127
Specifies the number of additional training frames
the local link partner delivers to ensure that the link
partner can correctly detect the local receiver state.
FEC Options
Include FEC
sublayer
Boolean • True
• False
False If this parameter is turned on, the IP core includes
logic to implement FEC
Set FEC_Ability
bit on power up
or reset
Boolean • True
• False
True
If this parameter is turned on, the IP core sets the
FEC ability bit (40GBASE-KR4 register offset 0xB0,
bit 16:
KR FEC enable
) on power up and reset.
This parameter is available if you turn on Include
FEC sublayer.
2-12 IP Core Parameters
UG-01172
2015.05.04
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