Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 187)

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D
2015.05.04
UG-01172 Subscribe
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Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore
Function User Guide Revision History
Table D-1: Document Revision History
Date Compatible ACDS
Version
Changes
2015.05.04 15.0
• User guide part number change from UG-01150 to UG-01172.
• Updated release-specific information for the software release v15.0.
• Added Synchronous Ethernet support for Arria 10 variations.
Documented new Enable SyncE parameter and new
clk_rx_
recover
output signal. Described expected usage in Clocks on page
3-51.
• Updated handling of received malformed packets, in LL 40-100GbE
IP Core Malformed Packet Handling on page 3-17, to incorporate
these changes in the IP core v15.0:
• The IP core asserts the
l_rx_error[0]
or
rx_error[0]
signal in the case of an unexpected control character that is not
an Error character.
• Both the LL 40GbE IP core and the LL 100GbE IP core handle
received malformed packets the same way.
• Updated the descriptions of
l_rx_error[0]
and
rx_error[0]
from PHY error to malformed packet error.
• Added new three-bit
l_rx_status
and
rx_status
signals on
the RX client interface. These signals explain the control frames that
the IP core passes to the client interface. Refer to Low Latency
40-100GbE IP Core RX Data Bus on page 3-20 and Low Latency
40-100GbE IP Core RX Data Bus Without Adapters (Custom
Streaming Interface) on page 3-24, and to new section Control
Frame Identification on page 3-19.
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