Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 87)

Figure 3-23: Example Boundary Clock with One Slave Port and Two Master Ports
You can implement a 1588 system in boundary clock mode using the LL 40-100GbE IP core with 1588
PTP functionality.
Packet
Parser
Packet
Parser
MAC TX
1588
MAC RX
1588
PHY
User Logic
User Logic
Packet Packet
Packet Packet Packet
rx_tod
Packet
BC Master 0
T1
T4
Packet
Parser
Packet
Parser
MAC TX
1588
MAC RX
1588
PHY
ToD
User Logic
User Logic CPU
Packet Packet
Packet Packet Packet
rx_tod
Packet
BC Slave
T3
T2
Cable Cable
Packet
Parser
Packet
Parser
MAC TX
1588
MAC RX
1588
PHY
User Logic
User Logic
Packet Packet
Packet Packet
BC Master 1
T1
T4
Cable
FPGA BC
Altera LL 40-100GbE IP Core
Altera LL 40-100GbE IP Core Altera LL 40-100GbE IP Core
Altera LL 40-100GbE IP Core
Packet
rx_tod
Packet
Related Information
IEEE website
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control
Systems Standard is available on the IEEE website.
PTP Receive Functionality
If you turn on Enable 1588 PTP in the Low Latency 40-100GbE parameter editor, the IP core provides a
96-bit (V2 format) timestamp with every packet on the RX client interface, whether it is a 1588 PTP
packet or not. The value on the timestamp bus (
rx_tod[95:0]
) is valid in the same clock cycle as the RX
SOP signal. The value on the timestamp bus is not the current timestamp; instead, it is the timestamp
from the time when the IP core received the packet on the Ethernet link. The IP core captures the
timestamp from the TOD module on
tod_rxmac_in
at the time it receives the packet on the Ethernet link,
and sends that timestamp to the client on the RX SOP cycle on the timestamp bus
rx_tod[95:0]
. User
logic can use this timestamp or ignore it.
3-42 PTP Receive Functionality
UG-01172
2015.05.04
Altera Corporation Functional Description
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