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Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual

Page 24

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Parameter

Type

Range

Default

Setting

Parameter Description

Status clock

rate

Frequenc

y range

100–162

MHz

100

MHz

Sets the expected incoming

clk_status

frequency.

The input clock frequency must match the frequency

you specify for this parameter.
The IP core is configured with this information:
• To ensure the IP core measures the link fail inhibit

time accurately.Determines the value of the Link

Fail Inhibit timer (IEEE 802.3 clause 73.10.2)

correctly.

• If

clk_status

frequency is not 100 MHz, to

adjust the PHY clock monitors to report accurate

frequency information.

This parameter determines the PHY Management

clock (MGMT_CLK) frequency in MHz parameter

of the underlying 10GBASE-KR PHY IP core.

However, the default value of the Status clock rate

parameter is different.

Auto-Negotiation

Enable Auto-

Negotiation

Boolean • True

• False

True

If this parameter is turned on, the IP core includes

logic to implement auto-negotiation as defined in

Clause 73 of IEEE Std 802.3ap–2007. If this parameter

is turned off, the IP core does not include auto-

negotiation logic and cannot perform auto-negotia‐

tion.
Currently the IP core can only negotiate to KR4

mode.

Link fail inhibit

time for 40Gb

Ethernet

Integer

(Unit:

ms)

500–510

ms

504 ms

Specifies the time before link status is set to FAIL or

OK. A link fails if the time duration specified by this

parameter expires before link status is set to OK. For

more information, refer to Clause 73 Auto-Negotia‐

tion for Backplane Ethernet in IEEE Standard

802.3ap–2007.
The 40GBASE-KR4 IP core asserts the

rx_pcs_ready

signal to indicate link status is OK.

Auto-Negotia‐

tion Master

String

• Lane 0

• Lane 1

• Lane 2

• Lane 3

Lane 0

Selects the master channel for auto-negotiation.

Pause ability–

C0

Boolean • True

• False

True

If this parameter is turned on, the IP core indicates

on the Ethernet link that it supports symmetric

pauses as defined in Annex 28B of Section 2 of IEEE

Std 802.3–2008.

2-10

IP Core Parameters

UG-01172

2015.05.04

Altera Corporation

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