Clock requirements for 40gbase-kr4 variations, External tx mac pll, Low latency 40-100gbe ip core testbenches – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 35: Clock requirements for 40gbase-kr4 variations -21, External tx mac pll -21, Low latency 40-100gbe ip core testbenches -21
TOD Module Signal
LL 40-100GbE IP Core Signal
tod_rxmclk[95:0]
(output)
tod_rxmac_in[95:0]
(input)
clk_txmac
(input)
clk_txmac
(output)
clk_rxmac
(input)
clk_rxmac
(output)
Related Information
•
External Time-of-Day Module for 1588 PTP Variations
on page 3-45
•
Low Latency 40-100GbE IP Core Example Project
Altera provides an example Quartus II project with the Low Latency 40-100GbE IP core. This example
project can compile and configure on an Altera device. In addition, for Arria 10 IP core variations, you
can use this example project to view one option for connecting the external TX PLL or TX PLLs in your
design.
•
1588 Precision Time Protocol Interfaces
on page 3-38
Clock Requirements for 40GBASE-KR4 Variations
In 40GBASE-KR4 IP core designs, you must drive the clocks for the two IP core register interfaces
(
reconfig_clk
and
clk_status
) from the same clock source.
External TX MAC PLL
If you turn on Use external TX MAC PLL in the LL 40-100GbE parameter editor, you must connect the
clk_txmac_in
input port to a clock source, usually a PLL on the device.
The
clk_txmac_in
signal drives the
clk_txmac
clock in the IP core TX MAC and PHY. If you turn off
this parameter, the
clk_txmac_in
input clock signal is not available.
The required TX MAC clock frequency is 312.5 MHz for 40GbE variations, and 390.625 MHz for 100GbE
variations. User logic must drive
clk_txmac_in
from a PLL whose input is the PHY reference clock,
clk_ref
.
Placement Settings for the Low Latency 40-100GbE IP Core
The Quartus II software provides the options to specify design partitions and LogicLock
™
regions for
incremental compilation, to control placement on the device. To achieve timing closure for your design,
you might need to provide floorplan guidelines using one or both of these features.
The appropriate floorplan is always design-specific, and depends on your full design.
Related Information
Describes incremental compilation, design partitions, and LogicLock regions.
Low Latency 40-100GbE IP Core Testbenches
Altera provides a testbench and an example project with most variations of the Low Latency 40-100GbE
IP core. The testbench is available for simulation of your IP core, and the example project can be run on
UG-01172
2015.05.04
Clock Requirements for 40GBASE-KR4 Variations
2-21
Getting Started
Altera Corporation