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Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual

Page 147

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Address

Name-

Description

Access

0x934

CNTR_RX_RUNT_LO

Number of received runt packets (lower 32 bits)
A run is a packet of size less than 64 bytes but greater than

eight bytes. If a packet is eight bytes or smaller, it is

considered a decoding error and not a runt frame, and the

IP core does not flag it nor count it as a runt.

RO

0x935

CNTR_RX_RUNT_HI

Number of received runt packets (upper 32 bits)
A run is a packet of size less than 64 bytes but greater than

eight bytes. If a packet is eight bytes or smaller, it is

considered a decoding error and not a runt frame, and the

IP core does not flag it nor count it as a runt.

RO

0x936

CNTR_RX_ST_LO

Number of received frame starts (lower 32 bits)

RO

0x937

CNTR_RX_ST_HI

Number of received frame starts (upper 32 bits)

RO

0x938–

0x93F

Reserved

0x940

RXSTAT_REVID

RX statistics module revision ID.

RO

0x941

RXSTAT_SCRATCH

Scratch register available for testing. Default value is 0x09. RW

0x942

RXSTAT_NAME_0

First 4 characters of IP core variation identifier string

"040gMacStats" or "100gMacStats"

RO

0x943

RXSTAT_NAME_1

Next 4 characters of IP core variation identifier string

"040gMacStats" or "100gMacStats"

RO

0x944

RXSTAT_NAME_2

Final 4 characters of IP core variation identifier string

"040gMacStats" or "100gMacStats"

RO

0x945

CNTR_RX_CONFIG

Bits [1:0]: Configuration of RX statistics counters:
• Bit [2]: Shadow request (active high): When set to the

value of 1, RX statistics collection is paused. The

underlying counters continue to operate, but the

readable values reflect a snapshot at the time the pause

flag was activated. Write a 0 to release.

• Bit [1]: Parity-error clear. When software sets this bit,

the IP core clears the parity bit

CNTR_RX_STATUS[0]

.

This bit (

CNTR_RX_CONFIG[1]

) is self-clearing.

• Bit [0]: Software can set this bit to the value of 1 to reset

all of the RX statistics registers at the same time. This

bit is self-clearing.

Bits [31:3] are Reserved.

RW

3-102

RX Statistics Registers

UG-01172

2015.05.04

Altera Corporation

Functional Description

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