Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 131)

Addr Name Bit Description HW Reset
Value
Access
0x602
TXSFC_NAME_
0
[31:0] First 4 characters of IP core variation
identifier string "40GSFCTxCSR" or
"100GSFCTxCSR".
RO
0x603
TXSFC_NAME_
1
[31:0] Next 4 characters of IP core variation
identifier string "40GSFCTxCSR" or
"100GSFCTxCSR".
RO
0x604
TXSFC_NAME_
2
[31:0] Final 4 characters of IP core variation
identifier string "40GSFCTxCSR" or
"100GSFCTxCSR".
RO
0x605
TX_PAUSE_EN
[N-
1:0] (9)
Enable the IP core to transmit pause frames
on the Ethernet link in response to a client
request through the
pause_insert_tx
input
signal or the
TX_PAUSE_REQUEST
register. If
your IP core implements priority-based flow
control, each bit of this field enables TX
pause functionality for the corresponding
priority queue.
Altera recommends that you signal a pause
request using the
pause_insert_tx
signal
rather than using the
TX_PAUSE_REQUEST
register.
N'b1 ...1 (1'b1
in each
defined bit)
RW
(9) N is the number of priority queues. If the IP core implements Ethernet standard flow control, N is 1.
3-86 Pause Registers
UG-01172
2015.05.04
Altera Corporation Functional Description
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