Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 124)

Address Name Bit Description HW
Reset
Value
Access
0x0D4
LD
coefficient
update[5:0],
Lane 0
[5:0] Reflects the contents of the first 16-bit word of
the training frame sent to Lane 0 from the local
device control channel. Normally, the bits in this
register are read-only; however, when you
override training by setting the
Ovride LP Coef
enable
control bit (0x0D0 bit [16]), these bits
become writeable. The following fields are
defined:
• [5: 4]: Coefficient (+1) update
• 2'b11: Reserved
• 2'b01: Increment
• 2'b10: Decrement
• 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding
as [5:4])
• [1:0]: Coefficient (-1) update (same encoding
as [5:4])
Before you can send these bits, you must enable
the override in 0x0D0 bit [16] and also signal a
new word in 0x0D1 bit [4].
For more information, refer to bit 10G BASE-KR
LD coefficient update register bits (1.154.5:0) in
Clause 45.2.1.80.3 of IEEE 802.3ap-2007.
RO/
RW
UG-01172
2015.05.04
LL 40GBASE-KR4 Registers 3-79
Functional Description Altera Corporation
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