Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 19)

IP Core Parameters
The Low Latency 40-100GbE parameter editor provides the parameters you can set to configure the Low
Latency 40-100GbE IP core and simulation testbenches.
Table 2-1: Low Latency 40-100GbE Parameters: Main Tab
Describes the parameters for customizing the 40-100GbE IP core on the Main tab of the 40-100GbE parameter
editor.
Parameter Type Range Default Setting Parameter Description
General Options
Device family String • Stratix V
• Arria 10
According to the
setting in the
project or IP
Catalog settings.
Selects the device family.
Protocol speed String • 40 GbE
• 100 GbE
100 GbE Selects the MAC datapath width.
Data interface String • Custom–ST
• Avalon–ST
Avalon–ST Selects the Avalon–ST interface or
the narrower, custom streaming
client interface to the MAC.
If you select the custom streaming
client interface, the Flow control
mode and Enable 1588 PTP
parameters are not available.
PCS/PMA Options
Enable CAUI4
PCS (1)(2)
Boolean • True
• False
False If turned on, the IP core is a 100GbE
CAUI-4 variation, with four
25.78125 Gbps transceiver PHY
links.
(1) The Enable CAUI4 PCS parameter is disabled when Protocol speed is set to 100GbE and Device family is
not Arria 10, and when Protocol speed is set to 40GbE. If the parameter is disabled, the IP core is
configured with the regular 100 Gbps PHY link option of 4 x 10.3125 Gbps or 10 x 10.3125 Gbps.
(2) For the Device family parameter, the CAUI-4 option requires the Arria 10 device.
UG-01172
2015.05.04
IP Core Parameters 2-5
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