Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 122)

Address Name Bit Description HW
Reset
Value
Access
Restart Link
training,
Lane 3
[3]
This bit is the equivalent of register 0xD0[1] for
Lane 3.
1'b0
RW SC
0x0D1
Updated TX
Coef new,
Lane 1
[5]
When set to 1, indicates that new link partner
coefficients are available to send. The LT logic
starts sending the new values set in 0xD4[7:0] to
the remote device. When set to 0, continues
normal operation. This bit self clears.
This override of normal operation can only
occur if 0xD0[16] (
Ovride LP Coef enable
)
has the value of 1. If 0xD0[16] has the value of 0,
this register field (0xD1[5]) has no effect.
Register bit 0xD1[4] refers to Lane 0. This bit is
the equivalent of register 0xD1[4] for Lane 1.
1'b0
RW SC
Updated TX
Coef new,
Lane 2
[6]
This bit is the equivalent of register 0xD1[5] for
Lane 2.
1'b0
RW SC
Updated TX
Coef new,
Lane 3
[7]
This bit is the equivalent of register 0xD1[5] for
Lane 3.
1'b0
RW SC
0x0D1
Updated RX
Coef new,
Lane 1
[9]
When set to 1, indicates that new local device
coefficients are available for Lane 1. The LT logic
changes the local TX equalizer coefficients as
specified in 0xE1[23:16]. When set to 0,
continues normal operation. This bit self clears.
This override of normal operation can only
occur if 0xD0[17] (
Ovride Local RX Coef
enable
) has the value of 1. If 0xD0[17] has the
value of 0, this register field (0xD1[9]) has no
effect.
Register bit 0xD1[8] refers to Lane 0. This bit is
the equivalent of register 0xD1[8] for Lane 1.
1'b0
RW
UG-01172
2015.05.04
LL 40GBASE-KR4 Registers 3-77
Functional Description Altera Corporation
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