Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 125)

Address Name Bit Description HW
Reset
Value
Access
LP
Coefficient
Update[5:0],
Lane 0
[21:16
]
Reflects the contents of the first 16-bit word of
the training frame most recently received on
Lane 0 from the control channel.
Normally the bits in this register are read only;
however, when training is disabled by setting low
the Link Training enable control bit (bit 0 at
offset 0xD0), these bits become writeable. The
following fields are defined:
• [5: 4]: Coefficient (+1) update
• 2'b11: Reserved
• 2'b01: Increment
• 2'b10: Decrement
• 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding
as [5:4])
• [1:0]: Coefficient (-1) update (same encoding
as [5:4])
Before you can send these bits, you must enable
the override in 0x0D0 bit [17] and also signal a
new word in 0x0D2 bit [8].
For more information, refer to bit 10G BASE-KR
LP coefficient update register bits (1.152.5:0) in
Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
0x0D5 Reserved [31:21
]
Reserved
0x0D6
LT VODMAX
ovrd, Lane 0
[4:0] Override value for the VMAXRULE parameter
on Lane 0. When enabled, this value substitutes
for the VMAXRULE to allow channel-by-
channel override of the device settings. This only
effects the local device TX output for the channel
specified.
This value must be greater than the
INITMAINVAL parameter for proper
operation. Note this will also override the
PREMAINVAL parameter value.
0x1C
(28
decim
al) for
simula
tion; 0
for
compil
ation
RW
LT VODMAX
ovrd Enable,
Lane 0
[5] When set to 1, enables the override value for the
VMAXRULE parameter stored in the
LT
VODMAX ovrd, Lane 0
register field.
1 for
simula
tion; 0
for
compil
ation
RW
3-80 LL 40GBASE-KR4 Registers
UG-01172
2015.05.04
Altera Corporation Functional Description
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