Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 71
Signal Name
Direction
Description
rx_fcs_error
Output
The current or most recent EOP byte is part of a frame with an
incorrect FCS (CRC-32) value. By default, the IP core asserts
rx_fcs_
error
in the same cycle as the
dout_eop
signal. However, if you turn
off Enable alignment EOP on FCS word in the LL 40-100GbE
parameter editor, the
rx_fcs_error
signal might lag the
dout_eop
signal for the frame.
Runt frames always force an FCS error condition. However, if a packet
is eight bytes or smaller, it is considered a decoding error and not a
runt frame, and the IP core does not flag it as a runt.
rx_fcs_valid
Output
When set, indicates that rx_fcs_error has a valid value in the current
clock cycle..
rx_status[2:0]
Output
Indicates the IP core received a control frame on the Ethernet link.
This signal identifies the type of control frame the IP core is passing
through to the client interface.
This signal is valid in EOP cycles only. To ensure you can identify the
corresponding packet, you must turn on Enable alignment EOP on
FCS word in the LL 40-100GbE parameter editor.
The individual bits report different types of received control frames:
• Bit [0]: Indicates the IP core received a standard flow control frame.
If the IP core is in standard flow control mode and the
cfg_fwd_
ctrl
bit of the
RX_PAUSE_FWD
register has the value of 0, this bit
maintains the value of 0.
• Bit [1]: Indicates the IP core received a priority flow control frame.
If the IP core is in priority flow control mode and the
cfg_fwd_
ctrl
bit of the
RX_PAUSE_FWD
register has the value of 0, this bit
maintains the value of 0.
• Bit [2]: Indicates the IP core received a control frame that is not a
flow control frame.
dout_valid
Output
The
dout_d
bus contents are valid. This signal is occasionally
deasserted due to clock crossing.
clk_rxmac
Output
RX MAC clock. The clock frequency should be 312.5 MHz in LL
40GbE IP cores, and 390.625 MHz in LL 100GbE IP cores. The
clk_
rxmac
clock is derived from the recovered CDR clock.
The data bytes use 100 Gigabit Media Independent Interface (CGMII-like) encoding. For packet payload
bytes, the
dout_c
bit is set to 0 and the
dout_d
byte is the packet data. You can use this information to
transmit out-of-spec data such as customized preambles when implementing non-standard variants of the
IEEE 802.3ba-2010 100G Ethernet Standard.
In RX preamble pass-through mode,
dout_c
has the value of 1 while the start byte of the preamble is
presented on the RX interface, and
dout_c
has the value of 0 while the remainder of the preamble
sequence (six-byte preamble plus SFD byte) is presented on the RX interface.
3-26
Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming
Interface)
UG-01172
2015.05.04
Altera Corporation
Functional Description