Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 190
Date
Compatible ACDS
Version
Changes
• Added information about how the IP core handles malformed
packets it receives. Previously the IP core did not terminate an
incoming packet if it receives an unexpected control character.
Changes are located in the new LL 40-100GbE IP Core Malformed
Packet Handling section.
• Added two new 64-bit statistics counters
RXOctets_OK
(offset
0x960) and
TxOctetsOK
(offset 0x860) to count the payload bytes
(octets) in received and transmitted frames with no FCS errors,
undersized, oversized, or payload length errors.
• Added four new signals in new octetsOK interface. These signals
provide per-frame information about the octet count in the two
new statistics counters: rx_inc_octetsOK, rx_inc_octetsOK_valid,
tx_inc_octetsOK, tx_inc_octetsOK_valid. Refer to new section
OctetOK Count Interface.
• Added new
CFG_PLEN_CHECK
register at offset 0x50A, to support
bit[4] of the new six-bit RX error signal.
• Added new link fault signals
unidirectional_en
and
link_fault_
gen_en
that provide status from the
LINK_FAULT_CONFIG
register.
• Described new method for handling module-specific signals when
the module is not included in your IP core variation. TX MAC
input clock, link fault signals, pause signals, and PTP signals are not
available in newly generated IP cores that do not include the
relevant module. However, for backward compatibility, if you
upgrade an IP core variation, link fault signals, pause signals, and
PTP signals in the earlier release of the IP core variation remain
available in the 14.1 version after upgrade.
• Updated PTP module description and signals for current IP core
version to support changes to the IP core 1588 PTP functionality.
Corrected description of the
tx_in_ptp_overwrite[1:0]
signal.
Improved usage description. If you turn on Enable 1588 PTP, the
PTP module has the following new features and requirements::
• You must instantiate a time-of-day module and connect it to the
IP core. Previously, this module was included in the IP core. The
change facilitates TOD module sharing among IP cores.
• Added new PTP signals
tod_rxmac_in
and
tod_txmac_in
to
receive the timestamps the TOD module generates in the two
clock domains.
• Removed TX PTP module TOD calculation registers at 0xB06
through 0xB08. The TOD module now provides the function‐
ality the registers supported in previous versions of the IP core.
• Added support for resetting the TCP checksum to zero if the
application does not recalculate it. The new feature adds two
new PTP signals
tx_in_zero_tcp
and
tx_in_tcp_offset
with
which the application communicates such a request to the IP
core.
• Clarified that IP core does not identify frames of eight bytes or less
as runts but instead as FCS errors.
D-4
Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User
Guide Revision History
UG-01172
2015.05.04
Altera Corporation
Additional Information