Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 104)

Signal Name Direction Interface
rx_status[2:0]
Output
dout_valid Output
pause_insert_tx[-1:0] Input Pause control and generation
interface
These signals are available in
new IP core variations that
include a flow control module.
In IP core variations that do not
include a flow control module,
but which you upgraded to the
v14.1 IP core, these signals are
tied low.
pause_receive_rx[-1:0] Output
remote_fault_status Output Link fault signaling interface
These signals are available in
new IP core variations that
include the link fault signaling
module. In IP core variations
that do not include the link fault
signaling module, but which you
upgraded to the v14.1 IP core,
these signals are tied low.
local_fault_status Output
unidirectional_en
Output
Link fault signaling interface,
Clause 66 status
These signals are available only
in IP core variations that include
the link fault signaling module.
link_fault_gen_en
Output
tx_inc_64 Output
TX statistics counter increment
vectors
These signals are available
whether or not your IP core
includes TX statistics counters.
tx_inc_127 Output
tx_inc_255 Output
tx_inc_511 Output
tx_inc_1023 Output
tx_inc_1518 Output
tx_inc_max Output
tx_inc_over Output
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core Signals 3-59
Functional Description Altera Corporation
Send Feedback