Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 47)

High Level System Overview
Figure 3-1: Low Latency 40GbE and 100GbE MAC and PHY IP Cores
Main blocks, internal connections, and external block requirements.
Low Latency 40- or 100-Gbps Ethernet MAC and PHY IP Core
TX
FIFO
TX
MAC
RX
MAC
PMA
PMA
RX
PCS
TX
Adapter
TX
PCS
XLAUI: 4 x 10.3125 Gbps or
CAUI: 10 x 10.3125 Gbps
CAUI-4: 4 x 25.78125 Gbps
Custom Streaming
Avalon-ST
Avalon-ST
Control and
Status Interface
Arria 10
Transceiver
Reconfiguration
Interface
(Arria 10 only)
Avalon-MM
Avalon-MM
RX
Adapter
Custom Streaming
Avalon-MM
Reconfiguration
Controller (Stratix V only)
PLL (Arria 10 only)
Low Latency 40- or 100-GbE
MAC
PHY
To optical module, backplane,
or separate device
From optical module, backplane,
or separate device
From
client application logic
To
client application logic
Low Latency 40-100GbE MAC and PHY Functional Description
The Altera Low Latency 40-100GbE IP core implements the 40-100GbE Ethernet MAC in accordance
with the IEEE 802.3ba 2010 40G and 100G Ethernet Standard. This IP core handles the frame encapsula‐
tion and flow of data between a client logic and Ethernet network via a 40-100GbE Ethernet PCS and
PMA (PHY).
In the transmit direction, the MAC accepts client frames, and inserts inter-packet gap (IPG), preamble,
start of frame delimiter (SFD), padding, and CRC bits before passing them to the PHY. The PHY encodes
the MAC frame as required for reliable transmission over the media to the remote end.
In the receive direction, the PHY passes frames to the MAC. The MAC accepts frames from the PHY,
performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of
the frame to the client. In RX preamble pass-through mode, the MAC passes on the preamble and SFD to
the client instead of stripping them out. In RX CRC pass-through mode (bit 1 of the
CRC_CONFIG
register
has the value of 1), the MAC passes on the CRC bytes to the client and asserts the EOP signal in the same
clock cycle with the final CRC byte.
3-2 High Level System Overview
UG-01172
2015.05.04
Altera Corporation Functional Description
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