Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 18)

1. In the IP Catalog (Tools > IP Catalog), select a target device family.
2. In the IP Catalog, locate and double-click the name of the IP core to customize. The New IP Variation
window appears.
3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation
settings in a file named .qsys (for Arria 10 variations) or .qip (for Stratix V
variations).
4. If your IP core targets the Arria 10 device family, you must select a specific device in the Device field.
The example project overwrites the selection with the device on the target board. However, if you do
not select a specific device, the Quartus II software does not generate your IP core correctly.
5. Click OK. The parameter editor appears.
6. Specify the parameters and options for your IP variation in the parameter editor, including one or
more of the following. Refer to your IP core user guide for information about specific IP core
parameters.
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for processing the IP core files in other EDA tools.
7. For Arria 10 variations, follow these steps:
a. Optionally, to generate a simulation testbench or example project, follow the instructions in
Generating the Low Latency 40-100GbE Testbench on page 2-28.
b. Click Generate HDL. The Generation dialog box appears.
c. Specify output file generation options, and then click Generate. The IP variation files generate
according to your specifications.
d. Click Finish. the parameter editor adds the top-level
.qsys
file to the current project automatically.
If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files
in Project to add the file.
8. For Stratix V variations, follow these steps:
a. Click Finish.
b. Optionally, to generate a simulation testbench or example project, follow the instructions in
Generating the Low Latency 40-100GbE Testbench on page 2-28.
After you click Finish and optionally follow the additional step to generate a simulation testbench
and example project, if available for your IP core variation, the parameter editor adds the top-
level .qsys file or top-level .qip file to the current project automatically. If you are prompted to
manually add the .qip file to the project, click Project > Add/Remove Files in Project to add the
file.
9. After generating and instantiating your IP variation, make appropriate pin assignments to connect
ports.
2-4 Specifying the Low Latency 40-100GbE IP Core Parameters and Options
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2015.05.04
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