Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 89
Figure 3-25: PTP Transmit Block Diagram
TX
Adapter
TX
PCS
TX
PMA
TX PTP
TOD Module
TX MAC
tx_data
ptp_data
tod_txmac_in
clk_txmac
ptp_pkt_out
tod_tx_clk_st2
If the IP core 1588 PTP module is in one-step mode, you must specify the offset of the timestamp in the
packet (
tx_in_ptp_offset[15:0]
), and provide an overwrite flag (
tx_in_ptp_overwrite[1:0]
) to tell
the IP core how to process the timestamp.
In one-step mode, the IP core either overwrites the timestamp information provided at the user-specified
offset with the packet exit timestamp, or adds the packet exit timestamp to the value at the specified offset,
or subtracts the current value at the specified offset from the packet exit timestamp, depending on the
value of
tx_in_ptp_overwrite[1:0]
. In addition, the IP core zeroes out the TCP checksum depending
on the value of
tx_in_zero_tcp
.
In two-step mode, the IP core ignores the values on the
tx_in_ptp_offset[15:0]
and
tx_in_ptp_overwrite[1:0]
signals. Instead of modifying the current timestamp in the packet, the IP
core transmits a two-step derived timestamp on the separate
tod_tx_clk_st2[95:0]
bus, when the IP
core begins transmitting the Ethernet frame. The value on the
tod_tx_clk_st2[95:0]
bus is the packet
exit timestamp.
tod_tx_clk_st2[95:0]
holds a valid value when the
ptp_pkt_out
signal is asserted.
When the IP core is in this mode, user logic is responsible for updating the TCP checksum.
In both one-step mode and two-step mode, the IP core calculates the packet exit timestamp:
exit timestamp = entry timestamp + IP core maintained expected latency + user-specified extra latency
• The expected latency through the IP core is a static value that is correct in most cases. The IP core
maintains this value internally.
• The IP core reads the user-specified extra latency from the
TX_PTP_EXTRA_LATENCY
register. This
option is provided for user flexibility.
Related Information
•
on page 3-103
•
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control
Systems Standard is available on the IEEE website.
3-44
PTP Transmit Functionality
UG-01172
2015.05.04
Altera Corporation
Functional Description