Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 185)

Property Low Latency 40-100GbE IP Core 40-100GbE IP Core v14.0
TX source address insertion Not available. The IP core transmits
the source address provided on the
TX client interface in the source
address field of the Ethernet frame.
Programmable in IP core
registers.
Pause frame control and
processing
You can request transmission of an
XOFF or XON pause frame by
asserting or deasserting a level input
signal. You configure registers to
specify the values in the pause
frame.
For backward compatibility, you
can also configure a register to
request transmission of a pause
frame. However, Altera
recommends you make the request
using the input signal instead.
Supports user-specified retransmis‐
sion hold-off time, to specify the
duration between repeat transmis‐
sion of XOFF frames.
Pause frame address filtering of
received pause frames compares the
incoming pause frame destination
address to the value in an IP core
register.
Two independent enable register
fields control the TX MAC
processing of incoming pause
frames on the Ethernet link and the
response to a user pause request. A
third enable register field controls
the RX MAC processing of
incoming pause frames on the
Ethernet link.
In IP core variations without
adapters, you can request
transmission of an XOFF or
XON pause frame by pulsing an
edge-triggered input signal.
Additional input signals specify
the values in the pause frame. In
all IP core MAC variations, you
can request transmission and
provide pause frame values by
configuring registers.
Does not support retransmission
hold-off time. You must control
retransmission of XOFF frames
in user logic. Asserting the edge-
triggered input signal or setting
the relevant pause request
register field generates a single
XOFF frame.
Pause frame address filtering of
received pause frames compares
the incoming pause frame
destination address to the
address of the IP core.
Two independent enable register
fields control the IP core
processing of incoming unicast
and multicast pause frames on
the Ethernet link. Does not
support register control of IP
core processing of incoming user
pause requests. To avoid the IP
core generating an outgoing
pause frame in response to a user
request, you must avoid
generating user pause requests.
Priority-based flow control Configurable in parameter editor. Not available.
C-4 Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.0
UG-01172
2015.05.04
Altera Corporation Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.0
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