Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 111)

Word Offset Register Description
0x50A Enable RX payload length checking register
Provides enable bit to determine whether the RX error signal flags payload lengths that do
not match the length field..
0x605–
0x60A
Transmit side pause registers
Accessible only if you set Flow control mode to the value Standard flow control or
Priority-based flow control.
0x700–
0x703
Receive side pause registers
Accessible only if you set Flow control mode to the value Standard flow control or
Priority-based flow control.
0x800–
0x837
Transmit side statistics registers
Accessible only if you turn on Enable TX statistics
0x845
Transmit statistics counters configuration register
CNTR_TX_CONFIG
Accessible only if you turn on Enable TX statistics
0x846
Transmit statistics counters status register
Accessible only if you turn on Enable TX statistics
0x900–
0x937
Receive side statistics registers
Accessible only if you turn on Enable RX statistics
0x945
Receive statistics counters configuration register
CNTR_RX_CONFIG
Accessible only if you turn on Enable RX statistics
0x946
Receive statistics counters status register
Accessible only if you turn on Enable RX statistics
0xA00–
0xA0A
TX 1588 PTP registers
Accessible only if you turn on Enable 1588 PTP
0xB00–
0xB05
RX 1588 PTP registers
Accessible only if you turn on Enable 1588 PTP
Related Information
• Control and Status Interface on page 3-49
• PHY Registers on page 3-67
• Link Fault Signaling Registers on page 3-70
Describes the fault link signaling and fault status signal registers.
• Low Latency 40-100GbE IP Core MAC Configuration Registers on page 3-83
3-66 Software Interface: Registers
UG-01172
2015.05.04
Altera Corporation Functional Description
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