Rx statistics registers – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
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RX Statistics Registers
The RX statistics registers count RX Ethernet traffic and errors. The 64-bit statistics registers are designed
to roll over, to ensure timing closure on the FPGA. However, these registers should never roll over if the
link is functioning properly. The statistics registers check the size of frames, which includes the following
fields:
• Size of the destination address
• Size of the source address
• Size of the data
• Four bytes of CRC
The RX statistics counters module is a synthesis option. The statistics registers are counters that are
implemented inside the CSR. When you turn on the Enable RX statistics parameter in the Low Latency
40-100GbE parameter editor, the counters are implemented in the CSR. When you turn off the Enable
RX statistics parameter in the Low Latency 40-100GbE parameter editor, the counters are not
implemented in the CSR, and read access to the counters returns read data equal to 0.
Reading the value of a statistics register does not affect its value. A configuration register at offset 0x945
allows you to clear all of the RX statistics counters.
To ensure that the counters you read are consistent, you should issue a shadow request to create a
snapshot of all of the RX statistics registers, by setting bit [2] of the configuration register at offset 0x945.
Until you reset this bit, the counters continue to increment but the readable values remain constant.
Table 3-29: Receive Side Statistics Registers
Address
Name-
Description
Access
0x900
CNTR_RX_
FRAGMENTS_LO
Number of received frames less than 64 bytes and
reporting a CRC error (lower 32 bits)
RO
0x901
CNTR_RX_
FRAGMENTS_HI
Number of received frames less than 64 bytes and
reporting a CRC error (upper 32 bits)
RO
0x902
CNTR_RX_JABBERS_
LO
Number of received oversized frames reporting a CRC
error (lower 32 bits)
RO
0x903
CNTR_RX_JABBERS_
HI
Number of received oversized frames reporting a CRC
error (upper 32 bits)
RO
0x904
CNTR_RX_FCS_LO
Number of received packets with FCS errors. This register
maintains a count of the number of pulses on the
l
rx_fcs_error
or
rx_fcs_error
output signal (lower 32
bits)
RO
0x905
CNTR_RX_FCS_HI
Number of received packets with FCS errors. This register
maintains a count of the number of pulses on the
l
rx_fcs_error
output signal (upper 32 bits)
RO
3-98
RX Statistics Registers
UG-01172
2015.05.04
Altera Corporation
Functional Description