Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 86
Figure 3-22: Software Flow Using Transparent Clock Mode System
This figure from the 1588 standard is augmented with the timestamp labels shown in the transparent
clock system figure. A precise description of the software requirements is beyond the scope of this
document. Refer to the 1588 standard.
UG-01172
2015.05.04
Implementing a 1588 System That Includes a LL 40-100GbE IP Core
3-41
Functional Description
Altera Corporation
This manual is related to the following products:
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