Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 123)

Address Name Bit Description HW
Reset
Value
Access
Updated RX
Coef new,
Lane 2
[10]
When set to 1, indicates that new local device
coefficients are available for Lane 2. The LT logic
changes the local TX equalizer coefficients as
specified in 0xE5[23:16]. When set to 0,
continues normal operation. This bit self clears.
This override of normal operation can only
occur if 0xD0[17] (
Ovride Local RX Coef
enable
) has the value of 1.
This bit is the equivalent of register 0xD1[9] for
Lane 2.
1'b0
RW
Updated RX
Coef new,
Lane 3
[11]
When set to 1, indicates that new local device
coefficients are available for lane 3. The LT logic
changes the local TX equalizer coefficients as
specified in 0xE9[23:16]. When set to 0,
continues normal operation. This bit self clears.
This override of normal operation can only
occur if 0xD0[17] (
Ovride Local RX Coef
enable
) has the value of 1.
This bit is the equivalent of register 0xD1[9] for
Lane 3.
1'b0
RW
0x0D2
Reserved [7:6] Reserved
[13:8] Register bits 0xD2[5:0] refer to Lane 0. These bits
are the equivalent of 0xD2[5:0] for Lane 1.
For
Link Training Frame lock Error, Lane
1
, if the tap settings specified by the fields of
0xE2 are the same as the initial parameter value,
the frame lock error was unrecoverable.
RO
[21:16
]
These bits are the equivalent of 0xD2[5:0] for
Lane 2.
For
Link Training Frame lock Error, Lane
2
, if the tap settings specified by the fields of
0xE6 are the same as the initial parameter value,
the frame lock error was unrecoverable.
RO
[29:24
]
These bits are the equivalent of 0xD2[5:0] for
Lane 3.
For
Link Training Frame lock Error, Lane
3
, if the tap settings specified by the fields of
0xEA are the same as the initial parameter value,
the frame lock error was unrecoverable.
RO
3-78 LL 40GBASE-KR4 Registers
UG-01172
2015.05.04
Altera Corporation Functional Description
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