Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 174)

Word Addr Bit R/W Name Description
0x4D3
9:0 RW
ber_time_frames
Specifies the number of training frames to examine
for bit errors on the link for each step of the
equalization settings. Used only when ber_time_k_
frames is 0.The following values are defined:
• A value of 2 is about 10
3 bytes
• A value of 20 is about 10 4 bytes
• A value of 200 is about 10 5 bytes
The default value for simulation is 2'b11. The
default value for hardware is 0.
19:10 RW
ber_time_k_frames
Specifies the number of thousands of training
frames to examine for bit errors on the link for
each step of the equalization settings. Set ber_time_
m_frames = 0 for time/bits to match the following
values:
• A value of 3 is about 10
7 bits = about 1.3 ms
• A value of 25 is about 10 8 bits = about 11ms
• A value of 250 is about 10 9 bits = about 11 0ms
The default value for simulation is 0. The default
value for hardware is 0x415.
29:20 RW
ber_time_m_frames
Specifies the number of millions of training frames
to examine for bit errors on the link for each step
of the equalization settings. Set ber_time_k_frames
= 4'd1000 = 0x43E8 for time/bits to match the
following values:
• A value of 3 is about 10
10 bits = about 1.3
seconds
• A value of 25 is about 10 11 bits = about 11
seconds
• A value of 250 is about 10 12 bits = about 110
seconds
UG-01172
2015.05.04
10GBASE-KR PHY Register Definitions B-15
Arria 10 10GBASE-KR Registers Altera Corporation
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