Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 158)

A single procedure generates both the testbench and the example project. The procedure varies depending
on your target device. To generate the testbench and example project:
1. Follow the steps in
Specifying the Low Latency 40-100GbE IP Core Parameters and Options on page
2-3 to parameterize your IP core.
2. If your IP core variation targets an Arria 10 device, in the Low Latency 40-100GbE parameter editor,
click the Example Design button to generate the testbench and example project for the IP core
variation you intend to generate.
Tip: You are prompted to locate the new testbench and example project in the directory
<working
directory>/alt_eth_ultra_0_example_design . You can accept the default path or modify the path to
the new testbench and example project.
3. Generate the IP core by clicking Generate HDL for Arria 10 variations or Generate for Stratix V
variations.
Note: If your IP core variation targets a Stratix V device, when prompted at the start of generation,
you must turn on Generate example design. Turning on Generate example design is the only
process that generates a functional testbench and a functional example project for Stratix V
variations.
When the IP core is generated in <working directory> , the testbench and example project are generated
in different locations depending on the device family your IP core variation targets.
• For Stratix V variations, the testbench and example project are generated in
<working directory>/<IP
core variation>_example_design/alt_eth_ultra .
• For Arria 10 variations, the testench and example project are generated in the directory you specify
in Step 2. If you do not modify the location text at the prompt, they are generated in <working
directory>/alt_eth_ultra_0_example_design
.
The directory with the testbench and example project has three subdirectories for Arria 10 variations and
two subdirectories for Stratix V variations:
•
example_testbench
• example_project
• ex_40g , ex_100g , or ex_100g_caui4 , for Arria 10 variations only
The ex_40g , ex_100g , or ex_100g_caui4 directory contains a copy of the IP core variation. The testbench
and example project for your Arria 10 IP core variation connect to the copy in this directory rather than
to the copy you generate in <working directory> .
Related Information
• Low Latency 40-100GbE IP Core Testbenches on page 2-21
Altera provides a testbench and an example project with most variations of the Low Latency 40-100GbE
IP core. The testbench is available for simulation of your IP core, and the example project can be run on
hardware. You can run the testbench to observe the IP core behavior on the various interfaces in
simulation.
• Low Latency 40-100GbE IP Core Example Project on page 5-1
Altera provides an example Quartus II project with the Low Latency 40-100GbE IP core. This example
project can compile and configure on an Altera device. In addition, for Arria 10 IP core variations, you
can use this example project to view one option for connecting the external TX PLL or TX PLLs in your
design.
Compiling the Low Latency 40-100GbE IP Core Example Project
UG-01172
2015.05.04
Compiling the Low Latency 40-100GbE IP Core Example Project A-5
Low Latency 40-100GbE IP Core Example Project Altera Corporation
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