Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 74)

Figure 3-18: The XOFF and XON Pause Frames for Standard Flow Control
XOFF Frame XON Frame
START[7:0] START[7:0]
PREAMBLE[47:0] PREAMBLE[47:0]
SFD[7:0] SFD[7:0]
DESTINATION ADDRESS[47:0] =
0x010000C28001 (3)
DESTINATION ADDRESS[47:0] =
0x010000C28001
SOURCE ADDRESS[47:0] SOURCE ADDRESS[47:0]
TYPE[15:0] = 0x8808 TYPE[15:0] = 0x8808
OPCODE[15:0] = 0x001 (standard FC) OPCODE[15:0] = 0x001 (standard FC)
PAUSE QUANTA[15:0] = 0xP1, 0xP2 (4) PAUSE QUANTA[15:0] = 0x0000
PAD[335:0] PAD[335:0]
CRC[31:0] CRC[31:0]
Figure 3-19: The XOFF and XON Pause Frames for Priority Flow Control
XOFF Frame XON Frame
START[7:0] START[7:0]
PREAMBLE[47:0] PREAMBLE[47:0]
SFD[7:0] SFD[7:0]
DESTINATION ADDRESS[47:0] =
0x010000C28001 (3)
DESTINATION ADDRESS[47:0] =
0x010000C28001
SOURCE ADDRESS[47:0] SOURCE ADDRESS[47:0]
TYPE[15:0] = 0x8808 TYPE[15:0] = 0x8808
OPCODE[15:0] = 0x0101 (PFC) OPCODE[15:0] = 0x0101 (PFC)
PRIORITY_ENABLE[15:0] (5) PRIORITY_ENABLE[15:0] (6)
TIME0[15:0] (7) TIME0[15:0] = 0x0000
... ...
TIME7[15:0] (7) TIME7[15:0] = 0x0000
PAD[207:0] PAD[207:0]
CRC[31:0] CRC[31:0]
(3) This is a multicast destination address.
(4) The bytes P1 and P2 are filled with the value configured in the
TX_PAUSE_QUANTA
register.
(5) Bit [n] has the value of 1 if the TIMEn field is valid.
(6) Bit [n] has the value of 1 if the XON request applies to priority queue n.
(7) The TIMEn field is filled with the value available in the
TX_PAUSE_QUANTA
register when the
TX_PAUSE_
QNUMBER
register holds the value of n.
UG-01172
2015.05.04
Congestion and Flow Control Using Pause Frames 3-29
Functional Description Altera Corporation
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