Phy status interface, Transceiver phy serial data interface, Low latency 40gbase-kr4 ip core variations – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 93: Phy status interface -48, Transceiver phy serial data interface -48, Low latency 40gbase-kr4 ip core variations -48
If the value in the
ptp_v2
field of the
TX_PTP_STATUS
register has the value of 0, the IP core outputs
timestamps in the V1 format in the lower 64 bits of the 96-bit timestamp bus:
• Bits [63:32]: Seconds (32 bits).
• Bits [31:0]: Nanoseconds (32 bits). This field overflows at 1 billion.
Related Information
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control
Systems Standard is available on the IEEE website.
PHY Status Interface
The
rx_pcs_ready
output signal is available to provide status information to user logic. This signal is
asserted when the RX lanes are fully aligned and ready to receive data.
The
tx_lanes_stable
output signal is available to provide status information to user logic. This signal is
asserted when the TX lanes are fully aligned and ready to transmit data.
Transceiver PHY Serial Data Interface
The core uses a 40-bit ×
operating at 10.3125 Gbps in the standard 40GbE and 100GbE variations and at 25.78125 Gbps in the
CAUI–4 variations. The
rx_serial
and
tx_serial
ports connect to the 10.3125 Gbps or 25.78125 Gbps
pins.Virtual lanes 0 and 1 transmit data on
tx_serial[0]
.
Low Latency 40GBASE-KR4 IP Core Variations
The LL 40GBASE-KR4 IP core supports low-level control of analog transceiver properties for link training
and auto-negotiation in the absence of a predetermined environment for the IP core. For example, an
Ethernet IP core in a backplane may have to communicate with different link partners at different times.
When it powers up, the environment parameters may be different than when it ran previously. The
environment can also change dynamically, necessitating reset and renegotiation of the Ethernet link.
The LL 40-100GbE IP core 40GBASE-KR4 variations implement the IEEE Backplane Ethernet Standard
802.3ap-2007. The LL 40-100GbE IP core provides this reconfiguration functionality in Arria 10 devices
by configuring each physical Ethernet lane with an Altera Backplane Ethernet 10GBASE-KR PHY IP core
if you turn on Enable KR4 in the 40-100GbE parameter editor. The parameter is available in variations
parameterized with these values:
• Device family: Arria 10
• Protocol speed: 40GbE
• Enable 1588 PTP: Off
3-48
PHY Status Interface
UG-01172
2015.05.04
Altera Corporation
Functional Description