Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 167)

Word Addr Bit R/W Name Description
0x4C3
15:0 RW
User base page low
The Auto Negotiation TX state machine uses these
bits if the Auto Negotiation base pages ctrl bit is
set. The following bits are defined:
• [15]: Next page bit
• [14]: ACK which is controlled by the SM
• [13]: Remote Fault bit
• [12:10]: Pause bits
• [9:5]: Echoed nonce which are set by the state
machine
• [4:0]: Selector
Bit 49, the PRBS bit, is generated by the Auto
Negotiation TX state machine.
21:16 RW
Override AN_
TECH[5:0]
AN_TECH
value with which to override the current
value. The following bits are defined:
• Bit-16 =
AN_TECH[0]
= 1000Base-KX
• Bit-17 =
AN_TECH[1]
= XAUI
• Bit-18 =
AN_TECH[2]
= 10Gbase-KR
• Bit-19 =
AN_TECH[3]
= 40G
• Bit-20 =
AN_TECH[4]
= CR-4
• Bit-21 =
AN_TECH[5]
= 100G
You must set 0x4C0 bit-5 for this to take effect .
25:24 RW
Override AN_
FEC[1:0]
AN_FEC
value with which to override the current
value. The following bits are defined:
• Bit-24 =
AN_ FEC [0]
= Capability
• Bit-25 =
AN_ FEC [1]
= Request
You must set 0x4C0 bit-5 for this to take effect.
30:28 RW
Override AN_
PAUSE[2:0]
AN_PAUSE value with which to override the
current value. The following bits are defined:
• Bit-28 =
AN_ PAUSE [0]
= Pause Ability
• Bit-29 =
AN_ PAUSE [1]
= Asymmetric
Direction
• Bit-30 =
AN_ PAUSE [2]
= Reserved
You must set 0x4C0 bit-5 for this to take effect.
0x4C4 31:0 RW
User base page high
The Auto Negotiation TX state machine uses these
bits if the Auto Negotiation base pages ctrl bit is
set. The following bits are defined:
• [29:5]: Correspond to page bit 45:21 which are
the technology ability.
• [4:0]: Correspond to bits 20:16 which are TX
nonce bits.
Bit 49, the PRBS bit, is generated by the Auto
Negotiation TX state machine.
B-8 10GBASE-KR PHY Register Definitions
UG-01172
2015.05.04
Altera Corporation Arria 10 10GBASE-KR Registers
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