Simulating with the ncsim simulator, Simulating with the vcs simulator, Simulating with the ncsim simulator -30 – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 44: Simulating with the vcs simulator -30
The ModelSim-AE simulator does not have the capacity to simulate this IP core.
Related Information
Optimizing the Low Latency 40-100GbE IP Core Simulation With the Testbenches
Instructions to improve simulation performance.
Simulating with the NCSim Simulator
To run the simulation in the supported versions of the NCSim simulation tool, follow these steps:
1. Change directory to the
_example_design/alt_eth_ultra/example_testbench
directory
or other location of your example testbench.
2. In the command line, type:
sh run_ncsim.sh
The example testbench will run and pass.
Related Information
Optimizing the Low Latency 40-100GbE IP Core Simulation With the Testbenches
Instructions to improve simulation performance.
Simulating with the VCS Simulator
To run the simulation in the supported versions of the VCS simulation tool, follow these steps:
1. Change directory to the
_example_design/alt_eth_ultra/example_testbench
directory
or other location of your example testbench.
2. In the command line, type:
sh run_vcs.sh
The example testbench will run and pass.
Related Information
Optimizing the Low Latency 40-100GbE IP Core Simulation With the Testbenches
Instructions to improve simulation performance.
Testbench Output Example: Low Latency 40-100GbE IP Core
This section shows successful simulation using the Low Latency 40-100GbE IP core testbench
(
_example_design/alt_eth_ultra/example_testbench/basic_avl_tb_top.v
for Stratix V
variations, or
/example_testbench/basic_avl_tb_top.v
for Arria 10 variations).
The testbench connects the Ethernet TX lanes to the Ethernet RX lanes, so that the IP core is in an
external loopback configuration. In simulation, the testbench resets the IP core and waits for lane
alignment and deskew to complete successfully. The packet generator sends ten packets on the Ethernet
TX lanes and the packet checker checks the packets when the IP core receives them on the Ethernet RX
lanes.
The successful testbench run displays the following output:
# *****************************************
# ** Starting TX traffic...
# **
# **
# ** Sending Packet 1...
# ** Sending Packet 2...
# ** Sending Packet 3...
# ** Sending Packet 4...
# ** Sending Packet 5...
2-30
Simulating with the NCSim Simulator
UG-01172
2015.05.04
Altera Corporation
Getting Started