Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function - Manual (Page 55)

Related Information
Avalon Interface Specifications
For more information about the Avalon-ST interface.
Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
When no adapters are used, the LL 40GbE custom interface bus width is 2 words (128 bits) and the LL
100GbE custom interface bus width is 4 words (256 bits). The LL 40GbE custom interface operates at
312.5 MHz and the LL 100GbE custom interface operates at 390.625 MHz.
Figure 3-6: TX Client to MAC Interface Without Adapters
The custom streaming interface bus width varies with the IP core variation. In the figure, = 2 for the
40GbE IP core and = 4 for the 100GbE IP core.
TX Client
Logic
din[*64-1:0]
din_sop[-1:0]
din_eop[-1:0]
din_eop_empty[*3-1:0]
din_req
tx_error[-1:0]
clk_txmac
TX MAC
din_idle[-1:0]
Table 3-3: Signals of the TX Client Interface Without Adapters
In the table, = 2 for the 40GbE IP core and = 4 for the 100GbE IP core. The signals are clocked by
clk_txmac
.
Signal Name Direction Description
din[*64-1:0] Input Data bytes to send in big-endian mode.
Most significant 64-bit word is in the higher-order bits. In 40GbE
variations, the most significant word is in bits [127:64] and in 100GbE
variations, the most significant word is in bits [255:192].
The Low Latency 40-100GbE IP core does not process incoming
frames of less than nine bytes correctly. You must ensure such frames
do not reach the TX client interface.
din_sop[-1:0] Input Start of packet (SOP) location in the TX data bus. Only the most
significant byte of each 64-bit word may be a start of packet. Bit 63 or
127 are possible for the 40GbE and bits 255, 191, 127, or 63 are possible
for 100 GbE.
Bit 0 of
din_sop
corresponds to the data word in
din[63:0]
.
3-10 Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming
Interface)
UG-01172
2015.05.04
Altera Corporation Functional Description
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