Megacore function -1, The altera – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 5
About the Low Latency 40- and 100-Gbps
Ethernet MAC and PHY MegaCore Function
1
2015.05.04
UG-01172
The Altera
®
Low Latency 40- and 100-Gbps Ethernet (40GbE and 100GbE) media access controller
(MAC) and PHY MegaCore
®
functions offer the lowest round-trip latency and smallest size to implement
the IEEE 802.3ba 40G and 100G Ethernet Standard with an option to support the IEEE 802.3ap-2007
Backplane Ethernet Standard.
The version of this product that supports Arria 10 devices is included in the Altera MegaCore IP Library
and available from the Quartus II IP Catalog.
Note: The full product name, Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore
Function, is shortened to Low Latency (LL) 40-100GbE IP core in this document. In addition,
although multiple variations are available from the parameter editor, this document refers to this
product as a single IP core, because all variations are configurable from the same parameter editor.
Figure 1-1: Low Latency 40GbE and 100GbE MAC and PHY IP Cores
Main blocks, internal connections, and external block requirements.
Low Latency 40- or 100-Gbps Ethernet MAC and PHY IP Core
TX
FIFO
TX
MAC
RX
MAC
PMA
PMA
RX
PCS
TX
Adapter
TX
PCS
XLAUI: 4 x 10.3125 Gbps or
CAUI: 10 x 10.3125 Gbps
CAUI-4: 4 x 25.78125 Gbps
Custom Streaming
Avalon-ST
Avalon-ST
Control and
Status Interface
Arria 10
Transceiver
Reconfiguration
Interface
(Arria 10 only)
Avalon-MM
Avalon-MM
RX
Adapter
Custom Streaming
Avalon-MM
Reconfiguration
Controller (Stratix V only)
PLL (Arria 10 only)
Low Latency 40- or 100-GbE
MAC
PHY
To optical module, backplane,
or separate device
From optical module, backplane,
or separate device
From
client application logic
To
client application logic
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