Getting started, Getting started -1 – Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Function User Manual
Page 15
Getting Started
2
2015.05.04
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The following sections explain how to install, parameterize, simulate, and initialize the Low Latency
40-100GbE IP core:
Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices
on page 2-2
The Low Latency 40-100GbE IP core that targets a Stratix V device is an extended IP core which is not
included with the Quartus II release. This section provides a general overview of the Altera extended IP
core installation process to help you quickly get started with any Altera extended IP core.
Installing and Licensing IP Cores
The Low Latency 40-100GbE IP core that targets an Arria 10 device is a standard Altera IP core in the
Altera IP Library.
Specifying the Low Latency 40-100GbE IP Core Parameters and Options
The LL 40-100GbE IP core for Arria 10 devices supports a standard customization and generation process
from the Quartus II IP Catalog. After you install and integrate the extended IP core in the ACDS release,
the LL 40-100GbE IP core for Stratix V devices also supports the standard customization and generation
process. The Low Latency 40-100GbE IP core is not supported in Qsys.
on page 2-5
The Low Latency 40-100GbE parameter editor provides the parameters you can set to configure the Low
Latency 40-100GbE IP core and simulation testbenches.
Files Generated for Stratix V Variations
The Quartus II software generates the following output for your Stratix V LL 40-100GbE IP core.
Files Generated for Arria 10 Variations
on page 2-14
The Quartus II software version 14.0 Arria 10 Edition and later generates the following IP core output file
structure when targeting Arria 10 devices.
Integrating Your IP Core in Your Design
Low Latency 40-100GbE IP Core Testbenches
Altera provides a testbench and an example project with most variations of the Low Latency 40-100GbE
IP core. The testbench is available for simulation of your IP core, and the example project can be run on
hardware. You can run the testbench to observe the IP core behavior on the various interfaces in
simulation.
Simulating the Low Latency 40-100GbE IP Core With the Testbenches
on page 2-27
Compiling the Full Design and Programming the FPGA
on page 2-31
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